1. Field of the Invention
The present invention relates to a level-conversion circuit and particularly relates to a level-conversion circuit for converting a small-amplitude-signal level and a semiconductor circuit including the level-conversion circuit and/or the small-amplitude-signal-level conversion circuit.
2. Description of the Related Art
In recent years, as the scale of integration and speed of large-scale integrated (LSI) circuits have become increasingly high, the amount of currents consumed by the LSI circuits has raised concerns. For example, where the integration scale of a DRAM increases to two times, the current consumption thereof does not increase to two times. Further, since clock frequencies increase, the increased frequency amount causes the current consumption to increase. Hitherto, measures for decreasing the power-source voltage have been taken, for example, for decreasing the current consumption. To achieve this, the capacities of transistors must be significantly improved, even though in many cases the capacities have already been improved to a level of saturation.
Various types of methods have been proposed, as low-power consumption technologies that require no process-technology development. For example, a reduction of the signal amplitude in long-distance wiring between blocks provided on a chip is significantly effective for reducing operation currents. In the case where a DRAM of about 256 Mbits is used, for example, about 45 percent of an entire burst current IDD4 corresponds to charge/discharge currents flowing in wiring on the chip. Therefore, where the charge/discharge currents in the wiring is decreased to one-second, that is to say, where the signal amplitude in the wiring is decreased to one-second, 22.5 percent of the burst current IDD4 is reduced.
However, several problems arise for decreasing the signal amplitude of the wiring to a small level. First, a level-conversion circuit is required of a circuit for receiving a small-amplitude signal. Hitherto, the level-conversion circuit operates at a low speed and uses the small-amplitude signal at many places, which sacrifices the characteristic of the circuit for receiving the small-amplitude signal. Therefore, the level-conversion circuits have been hardly used.
FIGS. 1A, 1B, and 1C show driver circuits for transmitting a small-amplitude signal and FIGS. 2A, 2B, and 2C show the waveforms thereof. In general, the output amplitude of a CMOS circuit is determined by the source voltage of a PMOS transistor on the load side and the source voltage of an NMOS transistor on the driver side. In the small-amplitude driver circuits of FIGS. 1A, 1B, and 1C, the source voltage of the PMOS transistor is made to be different from that of the NMOS transistor, so as to obtain a small-amplitude signal.
The small-amplitude driver circuit of FIG. 1A includes a power-source voltage VDD, an inverter circuit connected to a ground voltage VSS, a power-source voltage VDDL, and a driving inverter circuit connected to a ground voltage VSSH. The driving inverter circuit transmits the power-source voltage VDDL lower than the power-source voltage VDD to the source voltage of the PMOS transistor on the load side and transmits the ground voltage VSSH higher than the ground voltage VSS to the source voltage of the NMOS transistor on the driver side. Therefore, an input-signal amplitude VDD to VSS is transmitted, as a small amplitude VDDL to VSSH, as shown in FIG. 2A. At that time, a voltage Vgs between the gate and source of the PMOS transistor corresponds to an amplitude VDDL to VSS. Further, a voltage Vgs between the gate and source of the NMOS transistor corresponds to an amplitude VDD to VSSH. Since both voltages are small, an ON current Ids of each of the transistors is small and the capacity for charging and discharging wiring is small. Consequently, the signal-transmission speed of each of the transistors is low. Therefore, the threshold value (Vt) of each of the PMOS and NMOS transistors in an output stage is decreased, so as to be lower than the threshold value of an ordinary transistor. Thus, the ON current of each of the PMOS and NMOS transistors increases, so that the capacity for charging and discharging the wiring and the signal-transmission speed increase.
On the other hand, in each of small-amplitude driver circuits shown in FIGS. 1B and 1C, the voltage of either a transistor on the high-level side or a transistor on the low-level side is low. FIGS. 2B and 2C show the waveforms generated by the small-amplitude driver circuits shown in FIGS. 1B and 1C. In the small-amplitude driver circuit shown in FIG. 1B, the power-source voltage VDDL lower than the power-source voltage VDD is transmitted to the source voltage of the PMOS transistor on the load side and the amplitude level thereof is indicated, as VDDL to VSS. However, where a small-amplitude signal falls, the gate voltage of the NMOS transistor is the power-source voltage VDD and the source voltage thereof is the power-source voltage VSS. Consequently, the voltage Vgs corresponds to the amplitude VDD to VSS. However, where the small-amplitude signal rises, the gate voltage corresponds to the power-source voltage VSS, and the source voltage corresponds to the power-source voltage VDDL. Therefore, the voltage Vgs corresponds to the amplitude VDDL to VSS, the current Ids decreases, and the rising speed of an output signal becomes low. Accordingly, development has been made of a configuration for increasing the signal-transmission speed by decreasing the threshold value of only the PMOS transistor of the driver circuit.
FIGS. 1C and 2C show an example where the ground voltage VSSH higher than the ground voltage VSS is transmitted to the source voltage of the NMOS transistor, where the amplitude level is indicated, as VDDL to VSS. In this example, where a small-amplitude signal rises, the gate voltage of the PMOS transistor corresponds to the ground voltage VSS and the source voltage thereof corresponds to the power-source voltage VDD. Therefore, the voltage Vgs corresponds to the amplitude VDD to VSS. However, where the small-amplitude signal falls, the gate voltage corresponds to the power-source voltage VDD and the source voltage corresponds to the power-source voltage VDDL, so that the voltage Vgs corresponds to the amplitude VDD to VSSH. Consequently, the current Ids decreases and the falling speed of an output signal becomes low. Accordingly, development has been made of a configuration for increasing the signal-transmission speed by decreasing the threshold value of only the NMOS transistor of the driver circuit.
FIG. 3 shows a first known level-conversion circuit. The first known level-conversion circuit receives a small-amplitude signal (VDDL to VSS), as an input signal, and transmits a full-amplitude signal due to a ratio operation of an input stage. Therefore, the capacity of a PMOS transistor of an input-stage circuit is small and that of an NMOS transistor is large, so that the PMOS transistor and the NMOS transistor are made to perform the ratio operation. Accordingly, the falling speed of nodes N12 and N13 is high while the rising speed thereof is low. Therefore, even though the first known level-conversion circuit can generate an output signal with high speed at the time where an input signal IN rises, the first known level-conversion circuit generates an output signal with low speed at the time where the input signal IN falls. Specifically, a difference occurs between the signal rising speed and the signal falling speed. Accordingly, the first known level-conversion circuit cannot be used for the case where a signal needs to be caused to transition with high speed at both the falling time and the rising time.
FIG. 4 shows the configuration of a second known level-conversion circuit according to Japanese Unexamined Patent Application Publication No. 2002-135107 disclosing a technology for solving the problems of the above-described first known level-conversion circuit. The second known level-conversion circuit uses a method for preventing an output signal from being affected by the time delay generated due to the ratio operation of a level-conversion unit. In the second known level-conversion circuit configured in the same way as in the case of the first known level-conversion circuit, the rising speed of nodes N12 and N13 is high and the falling speed thereof is low due to the ratio operation of the PMOS transistor and the NMOS transistor. The second known level-conversion circuit uses a circuit technology for informing an output signal of only the input-signal rising that causes the second known level-conversion circuit to operate with high speed. However, since one of complementary input stages is slow, a through-current flow between the power-source voltage VDD and the ground voltage VSS is large.
Further, FIG. 5 shows the configuration of a third known level-conversion circuit that is disclosed in Japanese Unexamined Patent Application Publication No. 7-307661 and that is provided for a small-amplitude signal level (VDDL to VSSH). The third known level-conversion circuit operates by the power-source voltage VDDL that is lower than the power-source voltage VDD and the ground voltage VSSH higher than the ground voltage VSS, namely, the signal amplitude VDDL to VSSH. A receiver first stage of the third known level-conversion circuit comprises an inverter buffer circuit and a source-follower transistor for dropping the power-source voltage VDD. When the input signal IN rises and changes, a node N16 falls and a through-current flow is generated. At that time, the source-follower transistor drops the power-source voltage, so as to reduce the through-current flow. When the input signal falls and changes, the node N16 rises, so that the output signal OUT falls. Since the output signal OUT falls, a feedback PMOS transistor is turned on, so that the voltage of the node 16 drops to the power-source voltage VDD. Since the operation speed of the third known level-conversion circuit is easily affected by the ratio operation of the PMOS transistor and the NMOS transistor and the configuration in which a full-amplitude circuit receives a small-amplitude signal, the small-amplitude voltage level, the transistor threshold value, and the ratio of the receiver first stage need to be selected with caution so as to prevent the through-current flow being generated.